1. Field of the Invention
The present invention relates to a semiconductor device, a method for manufacturing the same, a method for generating mask data, a mask and a computer readable recording medium, and more particularly to a semiconductor device having multiple wiring layers, a method for manufacturing the same, a method for generating mask data, a mask, a computer readable recording medium.
2. Description of Related Art
Currently, multiple wiring layers are formed in order to realize higher circuit integration and further miniaturization of semiconductor devices. For example, multiple wiring layers are formed in the following manner. An interlayer dielectric layer is formed over a first wiring layer, and the interlayer dielectric layer is polished by a chemical-mechanical polishing method (hereinafter referred to as a “CMP method”). Then, a second wiring layer is formed over the interlayer dielectric layer, to thereby form multiple wiring layers.
As shown in FIG. 18, depending on a certain device design, first wiring layers 130a may be closely formed in one area and an isolated first wiring layer 130b may formed separated from such area on a first interlayer dielectric layer 120. Then, a second wiring layer 150 may be formed over the first wiring layers 130a and 130b through a second interlayer dielectric layer 140. In this case, the following problems occur.
When the second interlayer dielectric layer 140 is polished by a CMP method, a step difference is generated between an area of the second interlayer dielectric layer 140 where the first wiring layers 130a are closely formed and an area of the second interlayer dielectric layer 140 where the isolated first wiring layer 130b is formed. In other words, the area of the second interlayer dielectric layer 140 where the isolated first wiring layer 130b is formed is excessively polished compared to the area of the second interlayer dielectric layer 140 where the first wiring layers 130a are closely formed. This phenomenon occurs because the polishing rate differs depending on pattern densities of the wiring layers. More particularly, a polishing pressure is concentrated on the area of the second interlayer dielectric layer 140 where the isolated first wiring layer 130b is formed. As a result, the polishing rate of the second interlayer dielectric layer 140 in the area where the isolated first wiring layer 130b is formed becomes greater than the polishing rate of the second interlayer dielectric layer 140 in the area where the first wiring layers 130a are closely formed. Consequently, the area of the second interlayer dielectric layer 140 in the area where the isolated first wiring layer 130b is formed is excessively polished.
When the second interlayer dielectric layer 140 in the area where the isolated first wiring layer 130b is formed is excessively polished, problems occur. For example, the thickness of the second interlayer dielectric layer 140 becomes irregular. When the thickness of the second interlayer dielectric layer 140 becomes irregular, a step difference is generated in the second wiring layer 150 that is formed over the interlayer dielectric layer 140. When the step difference is generated in the second wiring layer 150, problems occur. For example, when the second wiring layer 150 is patterned by a photolithography, a designed pattern is not optically focused depending on areas, and the pattern may not be formed in such areas, or designed dimensions of the pattern may not be obtained even if the pattern is formed.
In order to solve the problems described above, one technique is proposed. According to the technique, dummy wiring layers 132 are formed in an area between the area where the first wiring layers 130a are densely formed and the area where the isolated first wiring layer 130b is formed, as shown in FIG. 19.
The technique for forming such dummy wiring layers is described in Japanese laid-open patent application HEI 4-218918, Japanese laid-open patent application HEI 10-335333, U.S. Pat. No. 4,916,514, U.S. Pat. No. 5,556,805, U.S. Pat. No. 5,597,668, U.S. Pat. No. 5,790,417 and U.S. Pat. No. 5,798,298.